This research activity addresses the problem of VLSI circuit layout. The research deals with the algorithms that are used inside VLSI design automation tools, also called computer-aided design (CAD) tools. VLSI stands for Very Large Scale Integration, which refers to those integrated circuits that contain more than 1 million transistors. The circuits designed may be general-purpose such as microprocessors and memories or application-specific integrated circuits (ASICs) which are designed for a narrow range of applications. Designing such a circuit is a difficult task. A first requirement is, of course, that a given specification is realized. Besides this, there are different entities that one would like to optimize. These entities can often be optimized simultaneously. The most important entities are: Area Minimization of the chip to increase the yield, Speed, Power dissipation, Design time and Testability.

Sample publications

• L. Rakai, L. Behjat, S. Areibi and Tamas Terlaky
  A Multi-level Congestion-Based Global Router
  Submitted to Hindawi, Journal of VLSI, July 2009.
• A. Nour, Z. Yang, M. Anis, S. Areibi, A. Vannelli, I. Elmasrry
  A Power-Efficient Multi-Pin ILP Based Routing Methodology
  IEEE Transactions on CAS, Accepted for Publication, Jan 2009.
• M. Xu, G. Grewal, S. Areibi, C. Obimbo and D. Banerji
  'Near-Linear Wirelength Estimation for FPGA Placement'.
  IEEE Canadian Conference on Electrical and Computer Engineering, CCECE'09, Newfoundland, Canada, May 2009.
• A. Yang, S. Areibi and A. Vannelli
  An ILP Based Hierarchical Global Routing Approach for VLSI ASIC Design
  Journal of Optimization Letters (Springer), Vol. 1, No. 3, pp: 281-297, June 2007.
• S. Areibi, X. Bao, G. Grewal, D. Banerji and P. Du
  Meta-Heuristic Based Techniques for FPGA Placement: A Study
  ACTA International Journal of Computers and Applications, Vol. 16, No. 1, pp:13-33, March 2009.
• S. Areibi, G. Grewal and D. Banerji and P. Du
  Hierarchical FPGA Placement
  Canadian Journal on Electrical and Computer Engineering, Vol. 32, No. 1, pp: 53-64, Winter 2007.
• S. Areibi and Z. Yang,
  Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering
  Journal of Evolutionary Computations, Special Issue on "Memetic Evolutionary Algorithms", pp: 327-353, Vol. 12, No. 3, Fall 2004.
• D. Kucar, S. Areibi and A. Vannelli,
  Hypergraph Partitioning Techniques
  Special Issue of Dynamics of Continuous, Discrete and Impulsive Systems Journal, pp: 341-369, Vol. 11, Issue 2-3, Feb 2004.
• P. Du, G. Grewal, S. Areibi and D. Banerji
  A Fast Hierarchical Approach to FPGA Placement
  Proceedings of the International Conference on Embedded Systems & Applications (ESA'04), Las Vegas Nevada, USA, pp: 497-503, June 2004
• P. Du, G. Grewal, S. Areibi and D. Banerji
  A Fast Adaptive Heuristic for FPGA Placement
  The 2nd Annual IEEE Northwest Workshop on Circuits and Systems, Montreal Canada, pp: 373-376, June 2004
• S. Areibi and A. Vannelli,
  Tabu Search: Implementation \& Complexity Analysis for Netlist Partitioning
  ISCA International Journal of Computers and Their Applications, pp: 211-232, Vol. 10, No. 4, December 2003.
• S. Areibi, A. Vannelli,
  Tabu Search: A Meta Heuristic for Netlist Partitioning
  VLSI Design Journal, pp: 259-283, Vol. 11, No. 3, 2000.

Researchers (CAD)

• Andy Ye (Ryerson University)
• Jason Anderson (University of Toronto)
• Cathy Gebotys (University of Waterloo)
• Andrew Kennings (University of Waterloo)
• Anthony Vannelli (University of Waterloo)
• Steve Wilton (University of British Columbia)
• Resve Saleh (University of British Columbia)
• Nicola Nicolici (McMaster University)
• Chunnhong Chen (University of Windsor)
• Dr. Mohammed Khalid (University of Windsor)
• Li Shang (Queens University)
• Laleh Behjat (University of Calgary)
• Asim Al-Khalili (Concordia University)
• Farid Najm (University of Toronto)
• Jonathan Rose (University of Toronto)
• Zvonko Vranesic (University of Toronto)

VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas. VLSI circuits are everywhere ... your computer, your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you. Some of my research is motivated by the challenges of Deep-Submicron (DSM) integrated processes. These challenges stem from previously ignorable physical phenomena (signal propagation delay, mounting leakage currents, parameter variations, signal integrity), as well as the growing complexity of realizable VLSI systems. The DSM challenge is therefore a rich source of unsolved problems in low-power and high-performance computing.

Sample publications

• W. Wang, S. Areibi, and M. Anis
  Modelling Leakage Power Reduction in VLSI as Optimization Problems
  Journal of Optimization and Engineering, Vol. 8, pp:129-162, May 2007.
• P.Ghafari, E. Mirhad, M. Anis and S. Areibi
  A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets
  IWSOC 2005, Banf, Alberta, Canada, pp: 368-371, Jul 2005
• W. Wang, M. Anis, and S. Areibi
  Fast Techniques for Standby Leakage Reduction in MTCMOS Circuits
  System On Chip Conference, SOC04, Santa Clara, pp: 21-24, Sep 2004
• M. Anis, S. Areibi, M. Elmsary
  Design and Optimization of Multi-Threshold CMOS (MTCMOS) Circuits
  IEEE Transaction on CAD, pp: 1324-1342, Vol. 22, No. 10, October 2003.
• M. Anis, S. Areibi, M. Mahmoud, M. Elmasry
  Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique
  IEEE Design Automation Conference (DAC02), New Orelans, pp: 480-486, June 2002

Researchers (VLSI)

• Mohab Anis (University of Waterloo)
• Manoj Sachdev (University of Waterloo)
• Andre Ivanov (University of British Colombia)
• Jamal Deen (McMaster University)
• Zine-Eddine Abid (Western Ontario)
• Stanley Simmons (Queens University)
• Graham Jullien (University of Calgary)
• Bruce Cockburn (University of Alberta)
• Krzysztof Iniewski (University of Alberta)
• Amirali Baniasadi (University of Victoria)

Sample publications

• S. Coe, S. Areibi, and M. Moussa
  A Hardware Memetic Accelerator for VLSI Circuit Partitioning
  International Journal of Computers and Electrical Engineering, Vol. 33, pp:233-248, May 2007.
• S. Coe, S. Areibi and M. Moussa
  A Genetic Local Search Hybrid Architecture for VLSI Circuit Partitioning
  Submitted for Publications in 16th International Conference on Microelectronics, Tunis, Tunisia, pp: --, Dec 2004

Researchers (Computer Architecture)

• Tor Aamodt (University of British Colombia)
• Naraig Manjikian (Queens University)
• Subramania Sudharsanan (Queens University)
• Wessam Hassanein (University of Calgary)
• Duncan Elliott (University of Alberta)
• Kin Fun Li (University of Victoria)

Reconfigurable Computing Systems are computers based on hardware, most of which can be arbitrarily defined to suit the needs of the particular problem to be solved. The goal of configurable computing is to achieve most of the performance of custom architectures while retaining most of the flexibility of general purpose computing. The main objective of this research activity is to design state of the art hardware accelerators to speedup the performance of combinatorial optimization heuristics and control algorithms based on Tabu Search, Genetic Algorithms, Neural Networks and Fuzzy Logic. Currently I am working on several advanced search heuristics for solving the VLSI circuit layout problem which require custom design hardware accelerators to obtain solutions in minimum CPU time. Some of the problems that can benefit from these advanced search techniques are graph partitioning, facility layout, global and detailed routing. The main idea is to divide the algorithm into sequentially executed stages. This process of "configure and execute" is repeated until the algorithm has completed its task.

Sample publications

• M. Ghazali, S. Areibi, G. Grewal, A. Erb, J. Spenceley
  'A Comparison of Hardware Acceleration Methods for VLSI Maze Routing'.
  Submitted to Symposium on Electronic Design Automation, Toronto, Canada, May 2009.
• A. Savich, M. Moussa and S. Areibi
  A Scalable Pipelined Architecture for Real-Time Computation of MLP-BP Neural Networks
  Submitted to ACM Transactions on Reconfigurable Technology and Systems, August 2009.
• A. Sghaier, S. Areibi, R. Dony
  Implementation Approaches Trade-offs for WiMax OFDM Functions on Reconfigurable Platforms
  ACM Transactions on Reconfigurable Technology and Systems, Accepted for Publication, Jan 2009.
• A. Sghaier, S. Areibi and R. Dony
  IEEE802.16-2004 OFDM Functions Implementation on FPGAs with Design Exploration.
  The International Conference on Field Programmable Logic and Applications (FPL), Germany, Sep 2008.
• A. Sghaier and S. Areibi and Robert Dony
  A Pipelined Implementation of OFDM Transmission on Reconfigurable Platforms.
  The Canadian Conference on Electrical and Computer Engineering, Niagra Falls, Canada, May 2008.
• A. Savich, M. Moussa and S. Areibi
  The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study
  IEEE Transactions on Artificial Neural Networks, Vol. 18, No. 1, pp: 240-252, January 2007.
• V. Pandya, S. Areibi and M. Moussa
  A Handel-C Implementation of the Back-Propagation Algorithm On FPGAs.
  International Conference on Reconfiguable Computing and FPGAs, ReConFig'05 Puebla, Mexico, pp: --, Sep 2005
• S. Areibi, M. Moussa and G. Koonar
  A Genetic Algorithm Hardware Accelerator for VLSI Circuit Partitioning
  ISCA International Journal of Computers and Their Applications, pp: 163--180, Volume 12, No 3, Sep 2005.
• S. Li, M. Moussa and S. Areibi
  Arithmetic Formats for Implementing Artificial Nerual Networks on FPGAs
  Canadian Journal on Electrical and Computer Engineering, Vol. 31, No.1 pp: 31-40, Winter 2006.
• M. Moussa, S. Areibi and K. Nichols
  On the Arithmetic Precision for Implementing Back-Propagation Networks on FPGA: A Case Study
  Book Chapter in FPGA Implementations of Neural Networks, Springer, The Netherlands, pp: 37-61, 2006.

Researchers (RCS)

• Dr. Peter Hallschmid (University of British Comlumbia)
• Dr. Andy Ye (Ryerson University)
• Dr. Ken Kent (University of New Brunswick)
• Dr. Bill Bishop (University of Waterloo)
• Dr. Wayne Loucks (University of Waterloo)
• Dr. Lev Kirischian (Ryerson University)
• Dr. Guy Lemieux (University of British Colombia)
• Dr. Witold Pedrycz (University of Alberta)
• Dr. Witold Kinsner (University of Manitoba)
• Dr. Robert McLeod (University of Manitoba)
• Dr. Voicu Groza (University of Ottawa)
• Dr. Daler Rahkmatov (University of Victoria)
• Dr. Mihai Sima (University of Victoria)
• Dr. Otmane Ait Mohamed (Concordia University)
• Dr. Stephen Brown (University of Toronto)
• Dr. Paul Chow (University of Toronto)
• Dr. Ahao, Yong (University of New Brunswick)
• RCS IN University of South Carolina
• RCS IN Ryerson University (Gul Khan)

Embedded controllers for reactive real-time applications are implemented as mixed software-hardware systems. These controllers utilize Micro-processors, Micro-controllers and Digital Signal Processors but are neither used nor perceived as computer. Generally, software is used for features and flexibility, while hardware is used for performance. Design of embedded systems can be subject to many different types of constraints, including timing, size, weight, power consumption, reliability, and cost. Current methods for designing embedded systems require to specify and design hardware and software separately. The main research contributions to this area is developing a methodology for specification, automatic synthesis, and validation of this sub-class of embedded systems. Design is done in a unified framework, with a unified hardware-software representation, so as to prejudice neither hardware nor software implementation. Previous techniques developed for VLSI Circuit Partitioning are modified to accommodate the difficulty of combining components that exhibit different characteristics.

Sample publications

• M. Ghazali, A. Elhossini, S. Areibi
  'HW/SW Co-Design Architecture Exploration for VLSI Maze Routing'.
  IEEE Canadian Conference on Electrical and Computer Engineering, CCECE'09, Newfoundland, Canada, May 2009.
• A. Elhossini and S. Areibi and R. Dony
  An Architecture Exploration Framework for DSP Applications.
  The Canadian Conference on Electrical and Computer Engineering, Niagra Falls, Canada, May 2008.
• F. Li and S. Areibi
  A Hardware/Software Co-Design Approach for VLSI Circuit Partitioning.
  Submitted to International Conference on Reconfiguable Computing and FPGAs, ReConFig'06, Puebla, Mexico, June 2006
• X. Li and S. Areibi
  A Hardware/Software Co-design Approach for Face Recognition
  Submitted for Publications in 16th International Conference on Microelectronics, Tunis, Tunisia, pp: --, Dec 2004

Researchers (H/S Co-Design)

• Gul Khan (Ryerson University)
• Andrew Morton (University of Waterloo)
• Dean McNeill (University of Manitoba)

Combinatorial optimization study problems, which are characterized by a finite number of feasible solutions, abound in everyday life, particularly in engineering design. An important and widespread area of applications concerns the efficient use of scarce resources to increase productivity. Typical engineering design problems relate to set covering, bin packing, knapsack packing, quadratic assignment, minimum spanning tree determination, vehicle routing and scheduling, facility location and so on. Engineering optimization and advanced search heuristics in the form of Tabu Search, Simulated Annealing, Genetic Algorithms and GRASP are indispensable working tools for industrial engineers and designers, as well as systems analysts, operations researchers, and management scientists working in manufacturing and related industries.I have proposed several novel techniques to reduce the complexity of problems via clustering and partitioning and also hybrid approaches that were very effective in solving combinatorial optimization problems in general and circuit layout in particular.

Sample publications

• A. Elhossini, S. Areibi and R. Dony
  Strength Pareto Parricle Swarm Optimization.
  The Third International Conference on Modeling, Simulation and Applied Optimization, ICMSAO'09, Sharjah, UAE, January 2009.
• A. Younes, S. Areibi and P. Calamai
  A Hybridized Evolutionary Algorithm For Dynamic Flexible Manufacturing Systems.
  The Third International Conference on Modeling, Simulation and Applied Optimization, ICMSAO'09, Sharjah, UAE, January 2009.
• K. Shaban, A. Younes, S. Areibi, M. Boos and F. Kuyvenhoven
  A Comparison of Meta-Heuristics for Flexible Manufacturing Systems.
  The Third International Conference on Modeling, Simulation and Applied Optimization, ICMSAO'09, Sharjah, UAE, January 2009.
• A. Younes, A. Elkamel, S. Areibi and A. Lohi
  Evolutionary Algorithms: What, When and How.
  The Third International Conference on Modeling, Simulation and Applied Optimization, ICMSAO'09, Sharjah, UAE, January 2009.
• A. Younes, K. Shaban, and S. Areibi
  Effective Memetic Algorithms for Scheduling in Flexible Manufacturing Systems
  Submitted to Elsevier, Journal of the Franklin Institute, May 2009.
• A. Elhossini, S. Areibi and R. Dony
  Strength Pareto Particle Swarm Optimization and Hybrid EA-PSO for Multi Objective Optimization
  Evolutionary Computation Journal, Accepted for Publication, Jan. 2009.
• A. Younes, A. Elkamel, S. Areibi
  How to Evaluate Meta Heuristic Algorithms effectively
  Book Chapter in: Chemical Engineering, Accepted for publication, 2008.
• A. Younes, A. Elkamel, S. Areibi
  Genetic Algorithms in Chemical Engineering: A tutorial
  Book Chapter in: Chemical Engineering, Accepted for publication, 2008.
• A. Younes, S. Areibi, P. Calamai, O. Basir
  Adapting Genetic Algorithms for Combinatorial Optimization Problems in Dynamic Environments
  Book Chapter in: Advances in Evolutionary Algorithms, ARS Publishing, Edited by: WiTold Kosinski, pp:207-230, ISBN978-953-7619-11-4, Sept. 2008.
• S. Areibi,
  Effective Exploration and Exploitation of the Solution Space via Memetic Algorithms
  Book Chapter in Recent Advances in Memetic Algorithms and Related Search Technologies, Springer-Verlag, Germany, pp: 161-182, 2005.
• D. Asmar, A. Elshamli and S. Areibi
  A Compartive Assessment of ACO Algorithms Within a TSP Environment
  DCDIS 2005, Guelph, Ontario, Canada, Guelph, Ontario, Canada, pp: --, Jul 2005.
• A. Elshamli, H. Abdullah, and S. Areibi
  Mobile Robots Path Planning Optimization in Dynamic Environments
  Submitted to IEEE Transactions on Robotics & Automation, August 2004.
• H. Homayounfar, S. Areibi and F. Wang
  An Advanced Island Based GA For Optimization Problems
  DCDIS Conference Guelph, Ontario, Canada, pp: 46-51, May 2003.
• A. Younes and H. Ghenniwa and S. Areibi,
  An Adaptive Genetic Algorithm for Multi-Objective Flexible Manufacturing Systems
  GECCO, New York, pp: 1241-1249, July 2002.

Researchers (Optimization)

• Dr. Bala Venkatesh (Ryerson University)
• Dr. Mohamed Bakr (McMaster University)
• Tamas Terlaky (McMaster University)
• Petr Musilek (University of Alberta)
• Sylvia Boyd (University of Ottawa)
• John W. Chinneck (Carleton University, S&CE)

Parallel and distributed computing systems offer the promise of a quantum leap in the computing power that can be brought to bear on many important problems. The potential for distributed processing exists whenever there are several computers interconnected in some fashion so that a program or procedure running on one machine can transfer control to a procedure running on another. The main objective in optimizing is twofold, minimizing the running time of the program and improving the efficiency of the algorithm.

Sample publications

• G. Lu and S. Areibi
  An Island Based GA Implementation for VLSI Standard Cell Placement
  Genetic and Evolutionary Computation COnference (GECCO-2004), Seattle Washington, USA, pp: 1138-1150, June 2004.
• S. Areibi and A. Vannelli ,
  Distributed Advanced Search Techniques for Circuit Partitioning.
  IEEE Canadian Conference on Electrical and Computer Engineering
  Waterloo, Ont, Canada, May 1998.

Researchers (Distributed Architectures)

• Ahmad Afsahi (Queens University)

Intelligent software agents are a unique generation of information society tools that independently perform various tasks on behalf of human user(s) or other software agents. The new possibility of information society requires the Development of new more intelligent methods, tools and theories for modelling/engineering of agent-based systems and technologies. Global competition and rapidly changing customer requirements are forcing major changes in the production sytles and configuration of manufacturing organizations. Agent technology provides a natural way to overcome such problems, and to design and implement distributed intelligent manufacturing environments. Our research focuses on the idea of integration from the perspective of rapidly deployable distributed systems as applied to distributed optimization problems and manufacturing systems.

Sample publications

• H. Homayounfar, F. Wang, S. Areibi
  Advanced P2P Architecture Using Autonomous Agents
  CAINE, San Diego California, pp: 115-118, Nov 2002.
• H. Ghenniwa and S. Areibi,
  Agent-Orientation for Evolutionary Computation
  ECOMS Workshop in New York, pp: 57-65, July 2002.

Researchers (Multi-Agent Systems)

• Hamada Ghenniwa (University of Western Ontario)
• Behrouz Homayoun (University of Calgary)
• Thomas Tran (University of Ottawa)

Due to the relentless improvement in silicon manufacturing technologies, the implementation of entire electronic systems on a single silicon chip is now a reality. Embedded systems and mobile devices (such as cellular telephones, audio-capable PDAs, and medical equipment such as hearing aids) are ubiquitous. These devices are often used in noisy environments such as cars, offices and public places. There is usually a reduction in the intelligibility and sound quality of these devices due to such noisy environment. Traditional design methods for noise reduction have focused on algorithm development followed by modifications for implementation on a general purpose digital signal processor (DSP). These DSPs are generally designed to optimize performance for a large class of signal processing applications. For high-performance embedded signal processing DSPs are very important, but, in some cases, DSPs alone cannot provide adequate amounts of computational power. Advancements in Field Programmable Gate Arrays (FPGAs) provide new options for DSP design engineers.

Sample publications

• D. Hermann and R. Dony and S. Areibi
  Oversampled Filter Bank Evaulation for Joint Subband Audio Processing and Coding.
  The Canadian Conference on Electrical and Computer Engineering, Niagra Falls, Canada, May 2008.
• D. Hermann, R. Dony and S. Areibi
  Window Based Prototype Filter Design for Highly Oversampled Filter Banks in Audio Appliations.
  IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP'07, Honolulu, USA, pp:405-408, April 2007.
• C. Freeman, R. Dony and S. Areibi
  Audio Environment Classification for Hearing Aids using ANNs with Windowed Input.
  First IEEE Symposium on Computational Intelligence in Image and Signal Processing CIISP'07, Honolulu, USA, pp:183-188, April 2007.
• C. Freeman, R. Dony and S. Areibi
  A Comparison of Classification Techniques for Audio Environment Classification
  International Journal of Information Technology and Intelligent Computing, Vol. 2, No. 3, pp: xxxx, June. 2007.
• A. Elhossini, S. Areibi and R. Dony
  An FPGA Implementation of the LMS Adaptive Filter for Audo Processing.
  Submitted to International Conference on Reconfiguable Computing and FPGAs, ReConFig'06, Puebla, Mexico, June 2006.

Researchers (DSP)

• Vijay Parsa, (University of Western Ontario)
• Awi-Yip Geoffrey Chan (Queens University)
• Saeed Gasor (Queens University)
• Rafik Goubran (Carleton University)
• Adrian Chan (Carleton University)
• Tyseer Aboulnasr (University of Ottawa)
• Miodrag Bolic (University of Ottawa)
• Peter Kabal (McGill University)